VLSI Mentors

STA

Why STA

Timing is the heartbeat of the chip. Every action performed inside the chip is driven by the clock pulse and the synchronous circuits work in tandem to give desired output at a desired speed. STA is one of the most important aspects of any design closure.

  • Course overview :

This course is a 12 week program

Every topic and sub-topics are discussed in detail with practical aspects

Program is 8 hour classroom session

Signoff STA concepts needed for design closure would be covered

Hands on classroom labs would be done to have hands on experience on STA topics

Enable learning through regular theory and lab assignments

Course completion Certificate after successful completion of program

  • Trainers details
 

Trainer 1

  • Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA
  • Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc.
  • Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups’
  • Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures
  • Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies
  • 500+ Engineers have been trained across the globe

Trainer 2

  • Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts
  • Executed Full Chip, Sub-System and block levels creating partitions
  • Have worked on Signoff like STA, PV, IR etc.
  • Experienced with 6 years in training who has held various levels of trainings
  • Trained about 650+ engineers.
  • Trainer brings in experience from multiple MNCs with about 16+ years of industry experience
  • Trainer is leading a team of 60+ engineers currently
  • Working on Full Chip and methodology development
  • Technology node expertise from 7nm till 250nm across various foundries
  • Strong hands on experience in Synopsys and Cadence tool sets
  • Strong in TCL and PERL
  • Syllabus

Standard Cell Libraries in detail

SDC, Multi-Mode, Multi Voltage constraints

Interconnect Parasitics and Models

Delay Calculation

PBA, GBA

Crosstalk Noise and Crosstalk Delay

Timing window

Clock Uncertainty/Latency

Clocks/Generated Clocks/Virtual clocks

IO Constraints/Timing Exceptions

Modelling the external environment (load/transition at IO Ports)

Timing Exceptions

Timing Analysis

Clock Gating emphasis on timing

Clock domain crossing

OCV, AOCV, POCV

DMSA

ECO generation

TCL constructs for Timing Signoff

 

  • Lab

Block level timing closure

Chip level timing closure

 

  • Who can attend

Engineers who want to get deeper knowledge on Timing analysis

Engineers who want to extend to STA from other streams like PD and Synthesis

Engineers who want to improve their scripting skills w.r.t. timing signoff

Engineers who want to understand ECO cycles for final design closure

Engineers who have completed PD training and want to get deeper into STA closure