{"id":254,"date":"2022-12-07T22:04:39","date_gmt":"2022-12-07T22:04:39","guid":{"rendered":"https:\/\/vmseo.vlsimentors.com\/?page_id=254"},"modified":"2022-12-07T22:13:42","modified_gmt":"2022-12-07T22:13:42","slug":"physical-design","status":"publish","type":"page","link":"https:\/\/vmseo.vlsimentors.com\/index.php\/physical-design\/","title":{"rendered":"Physical Design"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"254\" class=\"elementor elementor-254\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-5b221fb elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"5b221fb\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-40ba59d\" data-id=\"40ba59d\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-90535a9 elementor-widget elementor-widget-text-editor\" data-id=\"90535a9\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.8.1 - 13-11-2022 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><em>Why PD <\/em><\/p>\n<p><em>Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. Floorplan, placement of cells, clock building, routing of metals connecting the logic gates and meeting the desired timing frequency is the goal of Physical Design.<\/em><\/p>\n<p><em>&nbsp;<\/em><\/p>\n<ul>\n<li>Course overview :<\/li>\n<\/ul>\n<ol>\n<li>15+ week program<\/li>\n<li>Program covers all aspects of Netlist2GDS flow<\/li>\n<li>Every topic and sub-topics are discussed in detail with practical aspects and hands-on sessions<\/li>\n<li>Covers advanced concepts in Digital Design, CMOS, PnR flow, Signoff STA, Physical Verification, Low Power methodologies, Logic Equivalence Check and TCL scripting<\/li>\n<li>Our designs are co-developed with inputs from industry experts<\/li>\n<li>Soft Skill training<\/li>\n<li>Resume preparation support<\/li>\n<li>Regular assessment test to identify the areas that candidate needs to improve<\/li>\n<li>Enable learning through regular theory and lab assignments<\/li>\n<li>Course completion Certificate after successful completion of the program<\/li>\n<li>The path to industry would be very clear once this program is successfully completed<\/li>\n<li>Labs can be accessed through VPN (24&#215;7) from anywhere<\/li>\n<\/ol>\n<p><\/p>\n<ul>\n<li>Trainers details<\/li>\n<\/ul>\n<p><strong>Trainer 1<\/strong><\/p>\n<ul>\n<li>Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA<\/li>\n<li>Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc<\/li>\n<li>Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups\u2019<\/li>\n<li>Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures<\/li>\n<li>Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies<\/li>\n<li>500+ Engineers have been trained across the globe<\/li><\/ul>\n<p><strong>Trainer 2<\/strong><\/p>\n<ul>\n<li>Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts<\/li>\n<li>Executed Full Chip, Sub-System and block levels creating partitions<\/li>\n<li>Have worked on Signoff like STA, PV, IR etc.<\/li>\n<li>Experienced with 6 years in training who has held various levels of trainings<\/li>\n<li>Trained about 650+ engineers<\/li>\n<li>Trainer brings in experience from multiple MNCs with about 16+ years of industry experience<\/li>\n<li>Trainer is leading a team of 60+ engineers currently<\/li>\n<li>Working on Full Chip and methodology development<\/li>\n<li>Technology node expertise from 7nm till 250nm across various foundries<\/li>\n<li>Strong hands on experience in Synopsys and Cadence tool sets<\/li>\n<li>Strong in TCL and PERL<\/li>\n<\/ul>\n<p><\/p>\n<ul>\n<li>Syllabus<\/li>\n<\/ul>\n<p><strong>Module 1<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Advanced Digital Design<\/p>\n<p><strong>Module 2<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Introduction of CMOS Circuits<\/p>\n<p><strong>Module 2<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Introduction to Physical Design Flow &amp; Inputs<\/p>\n<p><strong>Module 3<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Design Planning (Floor-plan)<\/p>\n<p><strong>Module 4<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Power-Routing<\/p>\n<p><strong>Module 5<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Static Timing Analysis<\/p>\n<p><strong>Module 6<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Pre-Placement &amp; Std-Cell Placement<\/p>\n<p><strong>Module 7<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Timing Optimization<\/p>\n<p><strong>Module 8<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; CTS &amp; Post-CTS Timing Optimization<\/p>\n<p><strong>Module 9<\/strong>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Routing<\/p>\n<p><strong>Module 10<\/strong>&nbsp;&nbsp;&nbsp;&nbsp; Sign-off Checks<\/p>\n<p><strong>Module 11<\/strong>&nbsp;&nbsp;&nbsp;&nbsp; Timing Closure &amp; ECO Implementation<\/p>\n<p><strong>Module 12<\/strong>&nbsp;&nbsp;&nbsp;&nbsp; Low-Power Implementation<\/p>\n<p><strong>Module 13<\/strong>&nbsp;&nbsp;&nbsp;&nbsp; Introduction to Advanced STA Topics<\/p>\n<p><strong>Module 14<\/strong>&nbsp;&nbsp;&nbsp;&nbsp; TCL Scripting<\/p>\n<p><strong>Module 15<\/strong>&nbsp;&nbsp;&nbsp;&nbsp; Final Projects (Multiple)<\/p>\n<p><\/p>\n<ul>\n<li>Lab<\/li>\n<\/ul>\n<p>Complex block level implementation<\/p>\n<p>Designs covering full PnR end to end.<\/p>\n<p><\/p>\n<ul>\n<li>Tools and Project Design<\/li>\n<\/ul>\n<p>Most prominent and widely used tools in the industry<\/p>\n<p><\/p>\n<ul>\n<li>Who can attend<\/li>\n<\/ul>\n<p>Engineering Graduates (B.Tech, B.E., BS)<\/p>\n<p>Engineering Post-Graduates (M.Tech, M.E., M.S.)<\/p>\n<p>Experienced Engineers who want to change their domain to Physical Design<\/p>\n<p>Experienced Engineers who want to improve their Physical Design skills<\/p>\n<p>College faculties who want to gain Industry knowledge<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Why PD Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. Floorplan, placement of cells, clock building, routing of metals connecting the logic gates and meeting the desired timing frequency is [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"om_disable_all_campaigns":false,"_mi_skip_tracking":false},"aioseo_notices":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v19.11 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Physical Design - VLSI Mentors<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/vmseo.vlsimentors.com\/index.php\/physical-design\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Physical Design - VLSI Mentors\" \/>\n<meta property=\"og:description\" content=\"Why PD Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. 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