{"id":23,"date":"2022-12-03T09:14:39","date_gmt":"2022-12-03T09:14:39","guid":{"rendered":"https:\/\/vmseo.vlsimentors.com\/?page_id=23"},"modified":"2022-12-07T21:56:06","modified_gmt":"2022-12-07T21:56:06","slug":"sta","status":"publish","type":"page","link":"https:\/\/vmseo.vlsimentors.com\/index.php\/sta\/","title":{"rendered":"STA"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"23\" class=\"elementor elementor-23\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-0baff2f elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"0baff2f\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-3074221\" data-id=\"3074221\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-4f71ac3 elementor-widget elementor-widget-text-editor\" data-id=\"4f71ac3\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.8.1 - 13-11-2022 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><em>Why STA<\/em><\/p><p><em>Timing is the heartbeat of the chip. Every action performed inside the chip is driven by the clock pulse and the synchronous circuits work in tandem to give desired output at a desired speed. STA is one of the most important aspects of any design closure.<\/em><\/p><ul><li>Course overview :<\/li><\/ul><p>This course is a 12 week program<\/p><p>Every topic and sub-topics are discussed in detail with practical aspects<\/p><p>Program is 8 hour classroom session<\/p><p>Signoff STA concepts needed for design closure would be covered<\/p><p>Hands on classroom labs would be done to have hands on experience on STA topics<\/p><p>Enable learning through regular theory and lab assignments<\/p><p>Course completion Certificate after successful completion of program<\/p><ul><li>Trainers details<\/li><\/ul><table width=\"100%\"><tbody><tr><td>\u00a0<\/td><\/tr><\/tbody><\/table><p><strong>Trainer 1<\/strong><\/p><ul><li>Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA<\/li><li>Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc.<\/li><li>Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups\u2019<\/li><li>Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures<\/li><li>Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies<\/li><li>500+ Engineers have been trained across the globe<\/li><\/ul><p><strong>Trainer 2<\/strong><\/p><ul><li>Comes with immense experience in the spectrum of Physical Design having done more than 25 tapeouts<\/li><li>Executed Full Chip, Sub-System and block levels creating partitions<\/li><li>Have worked on Signoff like STA, PV, IR etc.<\/li><li>Experienced with 6 years in training who has held various levels of trainings<\/li><li>Trained about 650+ engineers.<\/li><li>Trainer brings in experience from multiple MNCs with about 16+ years of industry experience<\/li><li>Trainer is leading a team of 60+ engineers currently<\/li><li>Working on Full Chip and methodology development<\/li><li>Technology node expertise from 7nm till 250nm across various foundries<\/li><li>Strong hands on experience in Synopsys and Cadence tool sets<\/li><li>Strong in TCL and PERL<\/li><\/ul><ul><li>Syllabus<\/li><\/ul><p>Standard Cell Libraries in detail<\/p><p>SDC, Multi-Mode, Multi Voltage constraints<\/p><p>Interconnect Parasitics and Models<\/p><p>Delay Calculation<\/p><p>PBA, GBA<\/p><p>Crosstalk Noise and Crosstalk Delay<\/p><p>Timing window<\/p><p>Clock Uncertainty\/Latency<\/p><p>Clocks\/Generated Clocks\/Virtual clocks<\/p><p>IO Constraints\/Timing Exceptions<\/p><p>Modelling the external environment (load\/transition at IO Ports)<\/p><p>Timing Exceptions<\/p><p>Timing Analysis<\/p><p>Clock Gating emphasis on timing<\/p><p>Clock domain crossing<\/p><p>OCV, AOCV, POCV<\/p><p>DMSA<\/p><p>ECO generation<\/p><p>TCL constructs for Timing Signoff<\/p><p>\u00a0<\/p><ul><li>Lab<\/li><\/ul><p>Block level timing closure<\/p><p>Chip level timing closure<\/p><p>\u00a0<\/p><ul><li>Who can attend<\/li><\/ul><p>Engineers who want to get deeper knowledge on Timing analysis<\/p><p>Engineers who want to extend to STA from other streams like PD and Synthesis<\/p><p>Engineers who want to improve their scripting skills w.r.t. timing signoff<\/p><p>Engineers who want to understand ECO cycles for final design closure<\/p><p>Engineers who have completed PD training and want to get deeper into STA closure<\/p>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-8820cf4 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"8820cf4\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-99124ca\" data-id=\"99124ca\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-d31135e elementor-widget elementor-widget-text-editor\" data-id=\"d31135e\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Why STA Timing is the heartbeat of the chip. Every action performed inside the chip is driven by the clock pulse and the synchronous circuits work in tandem to give desired output at a desired speed. STA is one of the most important aspects of any design closure. Course overview : This course is a [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"om_disable_all_campaigns":false,"_mi_skip_tracking":false},"aioseo_notices":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v19.11 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>STA - VLSI Mentors<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/vmseo.vlsimentors.com\/index.php\/sta\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"STA - VLSI Mentors\" \/>\n<meta property=\"og:description\" content=\"Why STA Timing is the heartbeat of the chip. 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