{"id":21,"date":"2022-12-03T09:14:11","date_gmt":"2022-12-03T09:14:11","guid":{"rendered":"https:\/\/vmseo.vlsimentors.com\/?page_id=21"},"modified":"2022-12-06T13:24:10","modified_gmt":"2022-12-06T13:24:10","slug":"physical-design-mentorship","status":"publish","type":"page","link":"https:\/\/vmseo.vlsimentors.com\/index.php\/physical-design-mentorship\/","title":{"rendered":"Physical Design Mentorship"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"21\" class=\"elementor elementor-21\">\n\t\t\t\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-0d3c126 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"0d3c126\" data-element_type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-758f53a\" data-id=\"758f53a\" data-element_type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t\t\t<div class=\"elementor-element elementor-element-dca230a elementor-widget elementor-widget-text-editor\" data-id=\"dca230a\" data-element_type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t<style>\/*! elementor - v3.8.1 - 13-11-2022 *\/\n.elementor-widget-text-editor.elementor-drop-cap-view-stacked .elementor-drop-cap{background-color:#818a91;color:#fff}.elementor-widget-text-editor.elementor-drop-cap-view-framed .elementor-drop-cap{color:#818a91;border:3px solid;background-color:transparent}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap{margin-top:8px}.elementor-widget-text-editor:not(.elementor-drop-cap-view-default) .elementor-drop-cap-letter{width:1em;height:1em}.elementor-widget-text-editor .elementor-drop-cap{float:left;text-align:center;line-height:1;font-size:50px}.elementor-widget-text-editor .elementor-drop-cap-letter{display:inline-block}<\/style>\t\t\t\t<p><strong><span style=\"text-decoration: underline;\">COURSE<\/span>\u00a0<span style=\"text-decoration: underline;\">HIGHLIGHTS:<\/span><\/strong><br \/>\u2022 Trainers with 20+ years of Industry and 15+ years of teaching experience.<br \/>\u2022 Make-Flow Based Learning ( Industry uses Make-flow )<br \/>\u2022 Excellent coverage of concepts along with practical labs.<br \/>\u2022 24\/7 Lab access with VPN\/VNC.<br \/>\u2022 SYNOPSYS tools ( DC, ICC2, Fusion Compiler, PrimeTime).<br \/>\u2022 Placement assistance till you get placed.<br \/>\u2022 Option to attend the classes again in the next batch without any payment.<br \/>\u2022 Trainer has trained 1000+ Engineers worldwide.<br \/>\u2022 Resume preparation, interview guidance and placement support.<br \/>\u2022 Grooming the candidates for the written test &amp; interview.<br \/>\u2022 Freedom to update the course syllabus.<br \/>\u2022 Access the tools from anywhere &amp; anytime.<\/p><p><strong>Tools<\/strong> : <strong>(Synopsys Tools<\/strong> &#8211;\u00a0<strong>Latest Versions)<\/strong><br \/>\u2022 Design Compiler<br \/>\u2022 IC-Compiler 2<br \/>\u2022 Fusion-Compiler<br \/>\u2022 Star-RC<br \/>\u2022 PrimeTime<br \/>\u2022 Formality<\/p><p><strong>Syllabus<\/strong> : (<strong>PD<\/strong> \u2013 <strong>Mentorship) <\/strong><\/p><ul><li><strong>Basics:<\/strong><br \/>\u25cb Module 1: Digital Circuit Design<br \/>\u25cb Module 2: CMOS Circuit &amp; Layout Design<br \/>\u25cb Module 3: Linux Operating System<br \/>\u25cb Module 4: ASIC\/SOC Design flow<br \/>\u25cb Module 5: PDK and Technology Library<br \/>\u25cb Module 6: Standard Cell &amp; Macro Libraries<br \/>\u25cb Module 7: Timing Constraint ( SDC ) Development<br \/>\u25cb Module 8: Static Timing Analysis<\/li><\/ul><ul><li><strong>Implementation:<\/strong><br \/>\u25cb Module 9: RTL Synthesis<br \/>\u25cb Module 10: Pre-Layout STA<br \/>\u25cb Module 11: Introduction to DFT<br \/>\u25cb Module 12: Introduction to Physical Design Flow<br \/>\u25cb Module 13: Design Planning (Floorplan)<br \/>\u25cb Module 14: Power-Routing<br \/>\u25cb Module 15: Physical Cells Placement &amp; Std-Cell Pre-Placement<br \/>\u25cb Module 16: Std-Cell Placement<br \/>\u25cb Module 17: Scan-Chain Re-Ordering<br \/>\u25cb Module 18: Pre-CTS Timing Analysis &amp; Optimization<br \/>\u25cb Module 19: CTS<br \/>\u25cb Module 20: Post-CTS Timing Analysis &amp; Optimization<br \/>\u25cb Module 21: Routing<\/li><\/ul><ul><li><strong>SignoffChecks:<\/strong><br \/>\u25cb Module 22: Physical Verification<br \/>\u25cb Module 23: RC Extraction<br \/>\u25cb Module 24: Sign-off STA Checks<br \/>\u25cb Module 25: Timing Closure<br \/>\u25cb Module 26: ECO Implementation<br \/>\u25cb Module 27: Logical Equivalence Check<br \/>\u25cb Module 28: IR-Drop and Electromigration Analysis Flow<\/li><\/ul><ul><li><strong>Advanced Topics:<\/strong><br \/>\u25cb Module 29: Low Power Methodologies &amp; UPF<br \/>\u25cb Module 30: TCL Scripting<br \/>\u25cb Module 31: Advanced STA Topics<br \/>\u25cb Module 32: Introduction to Fin-FET &amp; Double-Patterning.<br \/>\u25cb Module 33: Introduction to 16nm, 7nm Technologies &amp; Floorplan Challenges<br \/>\u25cb Module 34: Make-Flow &amp; LSF<br \/>\u25cb Module 35: Final Projects ( Multiple Designs with different technologies )<\/li><\/ul><p>\u00a0<\/p><ul><li><strong>Placement<\/strong>\u00a0&amp; <strong>Career Guidance:<\/strong><br \/>\u25cb Soft-Skills Training<br \/>\u25cb Student Presentation<br \/>\u25cb Resume Preparation<br \/>\u25cb Interview Guidance<br \/>\u25cb Mock Interviews<\/li><\/ul>\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>COURSE&nbsp;HIGHLIGHTS: \u2022 Trainers with 20+ years of Industry and 15+ years of teaching experience. \u2022 Make-Flow Based Learning ( Industry uses Make-flow ) \u2022 Excellent coverage of concepts along with practical labs. \u2022 24\/7 Lab access with VPN\/VNC. \u2022 SYNOPSYS tools ( DC, ICC2, Fusion Compiler, PrimeTime). \u2022 Placement assistance till you get placed. \u2022 [&hellip;]<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"om_disable_all_campaigns":false,"_mi_skip_tracking":false},"aioseo_notices":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v19.11 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Physical Design Mentorship - VLSI Mentors<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" 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